Power Supply

Digital & Alalog

I used I/U transformers Sowter 8347 which works OK with 25 ohm I/U resistor. I had to increase value of this resistor about 9 times so now I have –0.25 dB not at 10 Hz but about at 90 Hz. In other words I do not have lower bass right now. I made a request for custom made DAC transformers from Sowter and expect to have them in several weeks.

P2P (Point to point diagram)

The Problem

I was told that all non-oversampling DACs have the same bug... At the recording side samples a made at the same time. Now look at CS8414 chart. We've got serial output: first goes out left channel, than right channel with 32 clock-beatings delay (signal FSYNK), which is T=1/(2*Fsmp) = 1/(2*44100)= 11.34 microseconds. It produces the phase shift between the channels:
360* 1000*0.00001134=4.08 degrees @ 1 kHz
and :
360*20000*0.00001134=81.7 degrees @ 20kHz.

It is definitely not significant @ 1 kHz and hard to say if it possible to hear such phase shift @ 20 kHz. May be somewhere in the middle? Nevertheless here is a solution of that problem.

The Solution

All we need is to hold somewhere the left channel data for the 32 clock beatings (signal CSK) and "feed" both DACs (left and right) at the same time. The simplest way is to use MC14557BCP shift register... I did not try this schema.

Sorry, this solution will not work. MC14557 just has too low clock frequency allowed to work in this schema OK.
Look:
Output receiver frequency for regular CD is 44.1 KHz * 64 tact beatings = 2.882 MHz
Max Clock Frequency allowed for 5v power supply is 1.7 MHz for MC14557
So it will not work. Sorry. My mistake. Schema needs faster IC
I have no plan to use shift register in near future. It could happen some time next year. Until than I have no reliable schema for this part of DAC.

A small tweak for Sony DVP-NS500V DVD Player